1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) devices wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly to a three-dimensional dynamic random access memory (DRAM) device structure with a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator.
2. Description of the Prior Art
The following references are typical of the state of the art of DRAMs with trench capacitors.
U.S. Pat. No. 4,353,086 issued Oct. 5, 1982 to Jaccodine et al entitled SILICON INTEGRATED CIRCUITS describes a dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mesa and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.
U.S. Pat. No. 4,327,476 issued May 4, 1982 to Iwai et al entitled METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES describes a method which comprises the steps of: forming at least one groove at a given location of a semiconductor substrate; laying an insulating film over the entire surface of the semiconductor substrate including the groove; depositing conductive material on the insulating layer to a thickness greater than half the width of an opening of the groove; and forming a MOS capacitor electrode of the conductor layer left in the groove by etching the deposited conductor layer until the insulating film other than its portion within the groove is exposed.
U.S. Pat. No. 4,462,847 issued July 31, 1984 to Thompson et al entitled FABRICATION OF DIELECTRICALLY ISOLATED MICROELECTRONIC SEMICONDUCTOR CIRCUITS UTILIZING SELECTIVE GROWTH BY LOW PRESSURE VAPOR DEPOSITION describes a method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern. A dielectric isolated circuit is fabricated, by such selective epitaxial growth, and a subsequent oxidation of both the mono- and polycrystalline deposits. By controlling the ratio of the deposition rates, and by controlling the oxidation step, the poly deposit is substantially fully converted to oxide, while the mono is only partly oxidized, leaving a substantially coplanar, isolated matrix of passivated monocrystalline areas in which to fabricate circuit components for interconnection.
In Japanese Pat. No. 58-137245, a technique is described to increase the area of an electrode without increasing the area of a plane by using the sidewall section of a groove dug into an Si substrate as the electrode surface of a capacitor. A field SiO.sub.2 film is formed selectively onto a Si substrate through a LOCOS method, an etched groove is formed into the substrate and a capacitor insulating film made of Si.sub.3 N.sub.4 is shaped onto these surfaces through a CVD method. The whole surface of the insulating film is coated with a plate represented by polycrystalline Si. A groove is buried with the same polycrystalline Si at that time. The plate is oxidized and a first inter-layer oxide film is formed, the Si.sub.3 N.sub.4 film and an SiO.sub.2 film are removed while using the oxide film as a mask, and a gate oxide film is formed through oxidation. A predetermined section is coated with a word line, and source-drain layers are formed to a section not coated with the plate and the gate through ion implantation, and a second inter-layer insulating film and the electrode are coated selectively.